Semiconductor chip (die, integrated circuit) is one of the most important hardware bases of modern information society. An electronic device integrates a plurality of chips; these chips mutually connect via channels, e.g., routes and/or transmission lines on circuit board, for signal exchange. By contents embedded in signal (e.g., data, message and/or command, etc), the chips in the electronic device can cooperate with each other to implement macro functions of the electronic device.
For receiving signal coming from other chip, each chip includes receiver circuit(s) to retrieve contents from received signal(s); because signal received is affected by various non-ideal factors (e.g., noise, low-pass nature of channel and interference between channels, etc), receiver circuit is demanded to evaluate quality of signal, and hence signal can be properly equalized, corrected and compensated. For example, BER is a common signal quality indication.
In a conventional signal quality evaluation solution, receiver circuit receives a test signal of predetermined patterns fed via channel, retrieves signal contents, compares if the retrieved signal matches the predetermined patterns, and accordingly evaluates BER. For example, assuming the test signal carries N bits; after receiving and retrieving of receiver circuit, if the retrieved contents contain Nx bits which fail to match the predetermined patterns, then a ratio Nx/N between the two numbers Nx and N is used as an evaluation of BER for signal receiving. In modern advanced signal interconnection standard, tolerable BER of receiver circuit is usually set to an order of 10^(−12) or 10^(−15), while bit rate of signal exchange is merely about 10^9 to 10^10 bits per second. Therefore, to obtain a statistically meaningful BER, such conventional art needs to spend a lot of time to feed huge amount of test bits.
Another conventional solution for evaluating quality of signal received is eye diagram monitoring. When receiver circuit receives an incoming signal and retrieves its contents, receiver circuit samples the signal in response to a normal timing, and determines whether sampled bit content is logic 0 or 1 according to a normal threshold level. To implement eye diagram monitoring, receiver circuit is arranged to further samples the received signal in response to a test timing (phase), and determines resultant bit content according to a test threshold level; if the bit content determined with a given test timing and a given test threshold level matches that determined with the normal timing and the normal threshold level, the given test timing and test threshold level are included in eye range of the eye diagram; if the two bit contents mismatch, the given test timing and test threshold level are excluded from eye range. By varying test timing and/or test threshold level, coverage of eye range can be probed and quality of signal received can be evaluated accordingly. For example, a larger coverage of eye range represents a better signal receiving quality, because it means that receiver circuit can tolerate greater timing shift and level variation.
However, since eye diagram monitoring needs to test many different combinations of testing timing and test threshold levels, such conventional art also needs a lot of time to scan the eye range. In addition, BER evaluation by eye diagram monitoring requires more information. Deriving BER from eye diagram not only needs to know threshold level variation (vertical extent) of eye range, but also needs information about signal amplitude; correct BER can be obtained only when both mentioned factors are gathered. In absence of amplitude detection, such conventional art can only be implemented by receiver circuit with AGC (auto gain control) capability, and thus can not be broadly adopted. Also, since eye diagram monitoring needs to fine-tune phase of test timing and amount of test threshold level, hardware complexity dramatically increases.